This is the first blog in a three-part series looking at ESD protection in mobile handsets.

The electrostatic discharge (ESD) phenomenon has been around since the beginning of time. Our first experience with ESD most often comes in childhood when you touch a metal doorknob on a dry wintry day. Zap, you get a shock — courtesy of electrostatic discharge. This momentary discomfort usually isn’t problematic for humans, but sensitive electrical circuits can be destroyed by even a small amount of ESD.  

Mobile designers continue to face challenges of when and how to address this natural phenomenon. This blog explains why system-level ESD protection matters, providing insight on test models and strategies to improve system-level ESD protection in mobile devices.
 

Testing for ESD models and waveforms

The human body and its clothing can store between 500 V and 2,500 V of electrostatic charge during a day, but a human can only feel ESD pulses that are between 3,000 and 4,000 V. This is far above the level that damages electronic circuits, even if a human can’t detect it.

Designers must address ESD at many points — at the component manufacturers, during their design phases and at the end of their design work. In short, ESD protection requires a multifaceted approach.

Typically, integrated circuit (IC) manufacturers design, test and qualify their ICs according to ESD industry standards. This protects against physical damage during IC production or assembly onto PC boards. The two tests that are typically used for ESD include the following:

• Human Body Model (HBM). This test simulates an ESD event in which a human body discharges the accumulated electrostatic charge by touching an IC. It’s modeled by a charged 100 pF capacitor and a 1.5 kΩ discharging resistor.

• Charged Device Model (CDM). This test simulates charging and discharging events that occur in production equipment and processes. The device acquires a charge through some frictional processes or electrostatic induction process and then abruptly touches a grounded object or surface.

While device-level testing helps provide a measure of ESD robustness for the IC, system-level testing measures the protection of the electronic devices when in the field (i.e., in the original equipment manufacturer [OEM] device or end product).

To display this concept further, the following table shows the differences between component testing and system-level IEC testing. As you can see, there’s a big difference — the system stress levels are higher. The takeaway: The system design must meet more stringent requirements than device-level designs.

 

The problem with inadequate testing

Performing system-level ESD tests during the development process can be problematic. For example, testing ESD on evaluation/incomplete board assemblies doesn't provide a full picture. Results on these assemblies don't guarantee the final result in the completed system.

Device-level ESD tests (i.e., HBM and CDM) were designed to generate repeatable and reproducible results for discrete components in a factory with the appropriate ESD controls. This is known as an ESD protected area (EPA). However, these tests aren’t intended to address the full range of real-world product-level ESD events outside of the EPA.
 

The key to product robustness: System-level ESD

Instead, the key to an ESD-robust system design is to consider the effects of ESD in the system. To obtain a system-level perspective, it’s paramount that designers understand and address the following:

The best approach: System-efficient ESD design (SEED)

System-efficient ESD design (SEED) is a system-level approach that considers the transient responses of all components in the system. SEED methodology also includes the physical effect of an IEC stress applied at the external port of the PC board on the IC pin. 

SEED is a co-design methodology that realizes both on-board and on-chip ESD protection. Using SEED, you analyze and achieve system-level ESD robustness. The approach requires a full understanding of interactions between external ESD pulses, full system-level board design, and device pin characteristics during an ESD stress event.

SEED methodology is the best approach for systematic and robust system-level ESD protection. As shown in the next figure, SEED uses the following to design system-level ESD protection:

• Quasi-static TLP current-voltage (I-V) curve data
• Transient simulations
• S-parameter PC board data
• IC I-V circuit measurements 

We'll go into the details of SEED in Part 2 and Part 3 of this blog series. But as a general introduction to SEED:

• The PC board’s ESD protection forms the primary protection, preventing physical damage to the IC or system.
• The on-chip protection serves a secondary protection role.

 
The fundamental concept of SEED is to limit the damaging ESD pulses from reaching the internal IC pins. Proper system-level ESD design is achieved by performing and analyzing an ESD system-level simulation.
 

Next up: ESD protection strategies for RF front-end designs

It’s no secret that it’s important to approach ESD strategically in your mobile designs. Doing so reduces design engineering cycle times, ESD failure and R&D expenses.

In the next post in this three-part blog series, we dig further into ESD protection components and different strategies to mitigate the effects of ESD on your mobile RF designs. Part 3 will explain how to use SEED methodology, simulation and modeling to determine your system-level ESD protection.